VLSI M.TECH/M.E IEEE 2018-19
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Project Title
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Abstract
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2018 IEEE TRANSACTIONS
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| 1. |
Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs |
XILINX |
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| 2. |
FIR Filter Realization via Deferred End-Around Carry Modular Addition |
XILINX |
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| 3. |
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Holomorphic Encryption |
XILINX |
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| 4. |
Advanced Compressor Tree Synthesis for FPGAs |
XILINX |
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| 5. |
Approximate DCT Image Compression using Inexact Computing |
XILINX |
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| 6. |
Compact CA-Based Single Byte Error Correcting Codec |
XILINX |
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| 7. |
DuCNoC: A High-Throughput FPGA-based NoC simulator using Dual-Clock Lightweight Router Micro-Architecture |
XILINX |
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| 8. |
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits |
XILINX |
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| 9. |
FIR Filter Realization via Deferred End-Around Carry Modular Addition |
XILINX |
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| 10. |
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications |
XILINX |
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| 11. |
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add |
XILINX |
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| 12. |
Bit stream Fault Injections (BiFI)– Automated Fault Attacks against SRAM-based FPGAs |
XILINX |
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| 13. |
An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications |
XILINX |
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| 14. |
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers |
XILINX |
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| 15. |
Detection and diagnosis of single faults in quantum circuits |
XILINX |
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| 16. |
Randomized Mixed-Radix Scalar Multiplication |
XILINX |
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| 17. |
VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability |
XILINX |
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| 18. |
YodaNN1: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration |
XILINX |
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| 19. |
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-based FPGAs |
XILINX |
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| 20. |
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA |
XILINX |
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| 21. |
GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs |
XILINX |
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| 22. |
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers |
XILINX |
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| 23. |
Unbiased Rounding for HUB Floating-point Addition |
XILINX |
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| 24. |
Accelerating FV Homomorphic scheme in FPGA with Karatsuba algorithm |
XILINX |
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| 25. |
FFT-based McLaughlin's Montgomery Exponentiation without Conditional Selections |
XILINX |
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| 26. |
A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security |
XILINX |
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| 27. |
STABLE: Stress-aware Boolean Matching to Mitigate BTI-induced SNM Reduction in SRAM-based FPGAs |
XILINX |
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| 28. |
Approximate Sum-of-Products Designs Based on Distributed Arithmetic |
XILINX |
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| 29. |
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators |
XILINX |
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| 30. |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates |
XILINX |
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| 31. |
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder |
XILINX |
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| 32. |
A Simple Yet Efficient Accuracy-Configurable Adder Design |
XILINX |
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| 33. |
Optimal Single Constant Multiplication Using Ternary Adders |
XILINX |
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| 34. |
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder |
XILINX |
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| 35. |
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata |
XILINX |
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| 36. |
A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation |
XILINX |
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| 37. |
Design of Area-Efficient and Highly Reliable RHBD I0T Memory Cell for Aerospace Applications |
TANNER/
MICROWIND |
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| 38. |
A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures |
TANNER/
MICROWIND |
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| 39. |
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits |
TANNER/
MICROWIND |
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| 40. |
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion |
TANNER/
MICROWIND |
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2018 IEEE JOURNALS/CONFERENCES
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| 41. |
An Approach to LUT Based Multiplier for Short Word Length DSP Systems |
XILINX |
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| 42. |
FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications |
XILINX |
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| 43. |
EEG Signal Denoising based on Wavelet Transform using Xilinx System Generator. |
XILINX |
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| 44. |
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters. |
XILINX |
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| 45. |
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter |
XILINX |
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| 46. |
VLSI Design Of Low-Cost And High-Precision Fixed-Point Reconfigurable FFT Processors |
XILINX |
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| 47. |
A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design |
XILINX |
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| 48. |
Chip Design for Turbo Encoder Module for In-Vehicle System |
XILINX |
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| 49. |
Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks |
XILINX |
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| 50. |
Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system |
XILINX |
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| 51. |
The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA |
XILINX |
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| 52. |
An Efficient VLSI Architecture for Convolution Based DWT Using MAC |
XILINX |
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| 53. |
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction |
XILINX |
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| 54. |
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing |
XILINX |
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| 55. |
Efficient Modular Adders based on Reversible Circuits |
XILINX |
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| 56. |
Binary To Gray Code Converter Implementation Using QCA |
XILINX |
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| 57. |
Power Efficient Approximate Multipliers in LMS Adaptive Filters |
XILINX |
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| 58. |
MAES: Modified Advanced Encryption Standard for Resource Constraint Environments |
XILINX |
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| 59. |
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) |
XILINX |
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| 60. |
High Performance Division Circuit using Reversible Logic Gates |
XILINX |
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| 61. |
A Novel Five-input Multiple-function QCA Threshold Gate |
TANNER/
MICROWIND |
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| 62. |
A Low-Power High-Speed Comparator for Precise Applications |
TANNER/
MICROWIND |
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| 63. |
A High Performance Gated Voltage Level Translator with Integrated Multiplexer |
TANNER/
MICROWIND |
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| 64. |
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop |
TANNER/
MICROWIND |
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| 65. |
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis |
TANNER/
MICROWIND |
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2017 IEEE TRANSACTIONS
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| 66. |
A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC |
XILINX | Download |
| 67. |
Probability-Driven Multibit Flip-Flop Integration With Clock Gating |
XILINX |
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| 68. |
Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication |
XILINX |
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| 69. |
Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA |
XILINX |
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| 70. |
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction |
XILINX |
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| 71. |
A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits |
XILINX |
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| 72. |
Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit |
XILINX |
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| 73. |
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials |
XILINX |
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| 74. |
Probabilistic Error Modeling for Approximate Adders |
XILINX |
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| 75. |
LFSR-Based Generation of Multicycle Tests |
XILINX |
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| 76. |
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs |
XILINX |
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| 77. |
An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA |
XILINX |
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| 78. |
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing |
XILINX |
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| 79. |
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA |
XILINX |
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| 80. |
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices |
XILINX |
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| 81. |
Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation |
XILINX |
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| 82. |
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping |
XILINX |
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| 83. |
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata |
XILINX |
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| 84. |
Overloaded CDMA Crossbar for Network-On-Chip |
XILINX |
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| 85. |
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder |
XILINX |
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| 86. |
Design of Power and Area Efficient Approximate Multipliers |
XILINX |
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| 87. |
An Efficient O(N) Comparison-Free Sorting Algorithm |
XILINX |
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| 88. |
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems |
XILINX |
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| 89. |
A General Digit-Serial Architecture for Montgomery Modular Multiplication |
XILINX |
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| 90. |
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations |
XILINX |
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| 91. |
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST |
XILINX |
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| 92. |
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication |
XILINX |
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| 93. |
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes. |
XILINX |
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| 94. |
On the VLSI Energy Complexity of LDPC Decoder Circuits |
XILINX |
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| 95. |
Reconfigurable Constant Multiplication for FPGAs |
XILINX |
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| 96. |
LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision |
XILINX |
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| 97. |
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division |
XILINX |
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| 98. |
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields. |
XILINX |
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| 99. |
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers |
TANNER/
MICROWIND |
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| 100. |
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique |
TANNER/
MICROWIND |
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| 101. |
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. |
TANNER/
MICROWIND |
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| 102. |
Register-Less NULL Convention Logic. |
TANNER/
MICROWIND |
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| 103. |
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops |
TANNER/
MICROWIND |
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| 104. |
Delay Analysis for Current Mode Threshold Logic Gate Designs |
TANNER/
MICROWIND |
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| 105. |
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage |
TANNER/
MICROWIND |
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